1. Field of the Invention
The present invention relates to high speed ASIC technology, and more particularly to a synchronous phase detector means for ASIC circuits.
2. Background Art
A typical phase detector circuit known in the art is illustrated in FIG. 1 and includes two flip-flops, which are clocked by two signals (Reference and VCO) having small frequency and phase errors. The logic circuit examines the rising edges of two signals, and the difference between them controls the VCO frequency through a loop filter in order to minimize the frequency and phase errors.
The first rising edge starts the active correction period, and it continues until the latter clock rises. The output of phase detector is active during this correction period (high or low depending on the error direction), and after the latter rising edge the logic is reset asynchronously.
In known high speed ASIC circuits this asynchronous resetting may cause problems, because the clear pulse disappears when the first flip-flop is cleared, and it cannot be certain if a short reset glitch works for both flip flops. Also, using separate frequencies may cause unwanted metastable states, which may cause uncorrect behavior.